View ADF4117_2540720.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adf4116/ADF4117/adf4118 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 rf pll frequency synthesizers features adf4116: 550 mhz ADF4117: 1.2 ghz adf4118: 3.0 ghz 2.7 v to 5.5 v power supply separate v p allows extended tuning voltage in 3 v systems selected charge pump currents dual modulus prescaler adf4116: 8/9 ADF4117/adf4118: 32/33 3-wire serial interface digital lock detect power-down mode fast lock mode applications base stations for wireless radio (gsm, pcs, dcs, cdma, wcdma) wireless handsets (gsm, pcs, dcs, cdma, wcdma) wireless lans communications test equipment catv equipment general description the adf4116 family of frequency synthesizers can be used to implement local oscillators in the up-conversion and down- conversion sections of wireless receivers and transmitters. they consist of a low-n oise digital pfd (phase frequency detector), a precision charge pump, a programmable reference divider, programmable a and b counters and a dual-modulus prescaler (p/p+1). the a (5-bit) and b (13-bit) counters, in conjunction with the dual modulus prescaler (p/p+1), implement an n divider (n = bp+a). in addition, the 14-bit reference counter (r counter), allows selectable refin frequencies at the pfd input. a complete pll (phase-locked loop) can be imple- mented if the synthesizer is used with an external loop ?ter and vco (voltage controlled oscillator). control of all the on-chip registers is via a simple 3-wire interface. the devices operate with a power supply ranging from 2.7 v to 5.5 v and can be powered down when not in use. functional block diagram reference fl o switch n = bp + a function latch prescaler p/p +1 13-bit b counter 5-bit a counter 14-bit r counter 21-bit input register r counter latch a, b counter latch phase frequency detector charge pump m3 m2 m1 high z mux muxout cp fl o av dd sd out 18 13 14 19 sd out from function latch 5 d g nd a g nd c e rf in b rf in a le data clk ref in cpgnd v p dv dd av dd lock detect adf4116/ADF4117/adf4118 load load
? rev. 0 adf4116/ADF4117/adf4118?pecifications 1 (av dd = dv dd = 3 v 10%, 5 v 10%; av dd v p 6.0 v; agnd = dgnd = cpgnd = 0 v; t a = t min to t max unless otherwise noted) parameter b version b chips 2 unit test conditions/comments rf characteristics rf input frequency see figure 22 for input circuit adf4116 45/550 45/550 mhz min/max ADF4117 0.045/1.2 0.045/1.2 ghz min/max adf4118 0.1/3.0 0.1/3.0 ghz min/max input level = ?0 dbm adf4118 0.2/3.0 0.2/3.0 ghz min/max maximum allowable prescaler output frequency 3 165 165 mhz max av dd, dv dd = 3 v 200 200 mhz max av dd, dv dd = 5 v rf input sensitivity ?5/0 ?5/0 dbm min/max av dd = 3 v ?0/0 ?0/0 dbm min/max av dd = 5 v refin characteristics reference input frequency 0/100 0/100 mhz min/max reference input sensitivity 4 ?/0 ?/0 dbm min/max ac-coupled. when dc-coupled: 0 to v dd max (cmos compatible) refin input capacitance 10 10 pf max refin input current 100 100 a max phase detector frequency 5 55 55 mhz max charge pump i cp sink/source high value 1 1 ma typ low value 250 250 a typ absolute accuracy 2.5 2.5 % typ i cp three-state leakage current 1 1 na max sink and source current matching 3 3 % typ 0.5 v v cp v p ?0.5 i cp vs. v cp 2 2 % typ 0.5 v v cp v p ?0.5 i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v inh , input high voltage 0.8 dv dd 0.8 dv dd v min v inl , input low voltage 0.2 dv dd 0.2 dv dd v max i inh /i inl , input current 1 1 a max c in , input capacitance 10 10 pf max reference input current 100 100 a max logic outputs v oh , output high voltage dv dd ?0.4 dv dd ?0.4 v min i oh = 500 a v ol , output low voltage 0.4 0.4 v max i ol = 500 a power supplies av dd 2.7/5.5 2.7/5.5 v min/v max dv dd av dd av dd v p av dd /6.0 av dd /6.0 v min/v max av dd v p 6.0 v i dd 6 (ai dd + di dd ) see figure 20 adf4116 5.5 4.5 ma max 4.5 ma typical ADF4117 5.5 4.5 ma max 4.5 ma typical adf4118 7.5 6.5 ma max 6.5 ma typical i p 0.4 0.4 ma max t a = 25 c low-power sleep mode 1 1 a typ
? rev. 0 adf4116/ADF4117/adf4118 parameter b version b chips 2 unit test conditions/comments noise characteristics adf4118 phase noise floor 7 ?70 ?70 dbc/hz typ @ 25 khz pfd frequency ?62 ?62 dbc/hz typ @ 200 khz pfd frequency phase noise performance 8 @ vco output adf4116 9 540 mhz output ?9 ?9 dbc/hz typ @ 1 khz offset and 200 khz pfd fre quency ADF4117 10 900 mhz output ?7 ?7 dbc/hz typ note 15 adf4118 10 900 mhz output ?0 ?0 dbc/hz typ note 15 ADF4117 11 836 mhz output ?8 ?8 dbc/hz typ @ 300 hz offset and 30 khz pfd frequ ency adf4118 12 1750 mhz output ?5 ?5 dbc/hz typ @ 1 khz offset and 200 khz pfd fre quency adf4118 13 1750 mhz output ?5 ?5 dbc/hz typ @ 200 hz offset and 10 khz pfd frequ ency adf4118 14 1960 mhz output ?4 ?4 dbc/hz typ @ 1 khz offset and 200 khz pfd fre quency spurious signals adf4116 9 540 mhz output ?8/?9 ?8/?9 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency ADF4117 10 900 mhz output ?0/?04 ?0/?04 dbc typ note 15 adf4118 10 900 mhz output ?1/?00 ?1/?00 dbc typ note 15 ADF4117 11 836 mhz output ?0/?4 ?0/?4 dbc typ @ 30 khz/60 khz and 30 khz pfd frequency adf4118 12 1750 mhz output ?8/?0 ?8/?0 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency adf4118 13 1750 mhz output ?5/?3 ?5/?3 dbc typ @ 10 khz/20 khz and 10 khz pfd fre quency adf4118 14 1960 mhz output ?0/?6 ?0/?6 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency notes 1 operating temperature range is as follows: b version: ?0 c to +85 c. 2 the b chip speci?ations are given as typical values. 3 this is the maximum operating frequency of the cmos counters. 4 av dd = dv dd = 3 v; for av dd = dv dd = 5 v, use cmos-compatible levels. 5 guaranteed by design. sample tested to ensure compliance. 6 av dd = dv dd = 3 v; rf in for adf4116 = 540 mhz; rf in for ADF4117, adf4118 = 900 mhz. 7 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 log n (where n is the n divider value). 8 the phase noise is measured with the eval-adf411xeb evaluation board and the hp8562e spectrum analyzer. the spectrum analyzer p rovides the refin for the synthesizer (f refout = 10 mhz @ 0 dbm). 9 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 540 mhz; n = 2700; loop b/w = 20 khz. 10 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 900 mhz; n = 4500; loop b/w = 20 khz. 11 f refin = 10 mhz; f pfd = 30 khz; offset frequency = 300 hz; f rf = 836 mhz; n = 27867; loop b/w = 3 khz. 12 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 1750 mhz; n = 8750; loop b/w = 20 khz. 13 f refin = 10 mhz; f pfd = 10 khz; offset frequency = 200 hz; f rf = 1750 mhz; n = 175000; loop b/w = 1 khz. 14 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 1960 mhz; n = 9800; loop b/w = 20 khz. 15 same conditions as above. speci?ations subject to change without notice. timing characteristics 1 limit at t min to t max parameter (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulsewidth note 1 guaranteed by design but not production tested. speci?ations subject to change without notice. (av dd = dv dd = 3 v 10%, 5 v 10%; av dd v p < 6.0 v; agnd = dgnd = cpgnd = 0 v; t a = t min to t max unless otherwise noted)
adf4116/ADF4117/adf4118 ? rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumu- late on the human body and test equipment and can discharge without detection. although the adf4116/ADF4117/adf4118 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 (t a = 25 c unless otherwise noted) av dd to gnd 3 . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v v p to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v p to av dd . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +5.5 v digital i/o voltage to gnd . . . . . . . . ?.3 v to v dd + 0.3 v analog i/o voltage to gnd . . . . . . . . . ?.3 v to v p + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c tssop ja thermal impedance . . . . . . . . . . . . . 150.4 c/w csp ja thermal impedance (paddle soldered) . . . . . . . . . . . . . . . . . . . . . . . . . 122 c/w (paddle not soldered) . . . . . . . . . . . . . . . . . . . . . . 216 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high-performance rf integrated circuit with an esd rating of < 2 kv and it is esd sensitive. proper precautions should be taken for handling and assembly. 3 gnd = agnd = dgnd = 0 v. transistor count 6425 (cmos) and 303 (bipolar). ordering guide model temperature range package description package option * adf4116bru ?0 c to +85 c thin shrink small outline package (tssop) ru-16 adf4116bcp ?0 c to +85 c chip scale package cp-20 ADF4117bru ?0 c to +85 c thin shrink small outline package (tssop) ru-16 ADF4117bcp ?0 c to +85 c chip scale package cp-20 adf4118bru ?0 c to +85 c thin shrink small outline package (tssop) ru-16 adf4118bcp ?0 c to +85 c chip scale package cp-20 * contact the factory for chip availability. warning! esd sensitive device clock data le le db20 (msb) db19 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 6 t 5 t 1 t 2 t 3 t 4 figure 1. timing diagram
adf4116/ADF4117/adf4118 5 rev. 0 pin function descriptions pin no. mnemonic function 1fl o fast lock switch output. this can be used to switch an external resistor to change the loop ?ter band- width. this will speed up locking of the pll. 2 cp charge pump output. when enabled, this provides the i cp to the external loop ?ter, which in turn drives the external vco. 3 cpgnd charge pump ground. this is the ground return path for the charge pump. 4 agnd analog ground. this is the ground return path for the prescaler. 5rf in b compleme ntary input to the rf prescaler. this point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. see figure 22. 6rf in a input to the rf prescaler. this small signal input is normally ac-coupled from the vco. 7av dd analog power supply. this may range from 2.7 v to 5.5 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must be the same value as dv dd . 8 ref in reference input. this is a cmos input with a nominal threshold of v dd /2 and an equivalent input resistance of 100 k ? . see figure 21. the oscillator input can be driven from a ttl or cmos crystal oscillator or it can be ac-c oupled. 9 dgnd digital ground. 10 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three- state mode. taking the pin high will power up the device depending on the status of the power-down bit f2. 11 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 21-bit shift register on the clk rising edge. this input is a high impedance cmos input. 12 data serial data input. the serial data is loaded msb ?st with the two lsbs being the control bits. this input is a high impedance cmos input. 13 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 muxout this multiplexer output allows either the lock detect, the scaled rf or the scaled reference frequency to be accessed externally. 15 dv dd digital power supply. this may range from 2.7 v to 5.5 v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . 16 v p charge pump power supply. this should be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5 v and used to drive a vco with a tuning range of up to 6 v. pin configurations tssop top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 fl o v p adf4116 ADF4117 adf4118 cp dv dd cpgnd muxout agnd le rf in b data rf in a clk av dd ce ref in dgnd chip scale package top view (not to scale) cpgnd agnd agnd rf in b rf in a muxout le data clk ce adf4116 ADF4117 adf4118 cp fl o v p dv dd dv dd av dd av dd ref in dgnd dgnd 1 2 3 4 5 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10
adf4116/ADF4117/adf4118 6 rev. 0 typical performance characteristics table i. s-parameter data for the adf4118 rf input (up to 1.8 ghz) keyword freq- param- data- impedance- unit type format ohms ghz s ma r 50 freq mags11 angs11 0.95 0.92087 ?6.961 1.00 0.93788 ?9.343 1.05 0.9512 ?0.134 1.10 0.93458 ?3.747 1.15 0.94782 ?4.393 1.20 0.96875 ?6.937 1.25 0.92216 ?9.6 1.30 0.93755 ?1.884 1.35 0.96178 ?1.21 1.40 0.94354 ?3.55 1.45 0.95189 ?6.786 1.50 0.97647 ?8.781 1.55 0.98619 ?0.545 1.60 0.95459 ?1.43 1.65 0.97945 ?1.241 1.70 0.98864 ?4.051 1.75 0.97399 ?6.19 1.80 0.97216 ?3.775 freq mags11 angs11 0.05 0.89207 ?.0571 0.10 0.8886 ?.4427 0.15 0.89022 ?.3212 0.20 0.96323 ?.1393 0.25 0.90566 ?2.13 0.30 0.90307 ?3.52 0.35 0.89318 ?5.746 0.40 0.89806 ?8.056 0.45 0.89565 ?9.693 0.50 0.88538 ?2.246 0.55 0.89699 ?4.336 0.60 0.89927 ?5.948 0.65 0.87797 ?8.457 0.70 0.90765 ?9.735 0.75 0.88526 ?1.879 0.80 0.81267 ?2.681 0.85 0.90357 ?1.522 0.90 0.92954 ?4.222 rf input frequency ghz 0 4.0 0.5 1.5 2.0 2.5 3.0 3.5 35 rf input power dbm 0 15 20 25 30 5 10 1.0 v dd = 3v v p = 3v t a = 40 c t a = 85 c t a = 25 c 40 45 figure 2. input sensitivity (adf4118) 2khz 1khz 900mhz +1khz +2khz v dd = 3v, v p = 5v i cp = 1ma pfd f requency = 200khz loop b andwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 22 reference level = 4.2dbm output power db 0 50 70 80 90 10 30 60 40 20 100 90.2dbc/hz figure 3. adf4 118 phase noise (900 mhz, 200 khz, 20 khz) 10db/division r l = 40dbc/hz rms noise = 0.64 100hz frequency offset from 900 mhz carrier 1mhz phase noise dbc/hz 40 80 100 50 70 60 90 110 120 130 140 0.64 rms figure 4. adf4118 integrated phase noise (900 mhz, 200 khz, 35 khz, typical lock time: 200 s) 10db/division r l = 40dbc/hz rms noise = 0.575 100hz frequency offset from 900 mhz carrier 1mhz phase noise dbc/hz 40 70 80 90 100 50 60 110 120 130 140 0.575 rms figure 5. adf4118 integrated phase noise (900 mhz, 200 khz, 20 khz, typical lock time: 400 s) 400khz 200khz 900mhz +200khz +400khz v dd = 3v, v p = 5v i cp = 1ma pfd f requency = 200khz loop b andwidth = 20khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 4 reference level = 3.8dbm output power db 0 50 70 80 90 10 30 60 40 20 100 91.5dbc figure 6. adf4118 reference spurs (900 mhz, 200 khz, 20 khz)
adf4116/ADF4117/adf4118 7 rev. 0 400khz 200khz 900mhz +200khz +400khz v dd = 3v, v p = 5v i cp = 1ma pfd frequency = 200khz loop b andwidth = 35khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 10 reference level = 4.2dbm output power db 0 50 70 80 90 10 30 60 40 20 100 90.67dbc figure 7. adf4118 reference spurs (900 mhz, 200 khz, 35 khz) 400khz 200khz 1750mhz +200khz +400khz v dd = 3v, v p = 5v i cp = 1ma pfd f requency = 30khz loop b andwidth = 5khz res. bandwidth = 10khz video bandwidth = 10khz sweep = 477ms averages = 25 reference level = 7.0dbm output power db 0 50 70 80 90 10 30 60 40 20 100 71.5dbc/hz figure 8. adf4118 phase noise (1750 mhz, 30 khz, 3 khz) 10db/division r l = 40dbc/hz rms noise = 2.0 100hz frequency offset from 1.75ghz carrier 1mhz phase noise dbc/hz 40 70 80 90 100 50 60 110 120 130 140 2.0 rms figure 9. adf4118 integrated phase noise (1750 mhz, 30 khz, 3 khz) 60khz 30khz 1750mhz +30khz +60khz reference level = 7.0dbm output power db 0 50 70 80 90 10 30 60 40 20 100 v dd = 3v, v p = 5v i cp = 5ma pfd f requency = 30khz loop b andwidth = 5khz res. bandwidth = 300hz video bandwidth = 300hz sweep = 4.2ms averages = 20 72.3dbc figure 10. adf4118 reference spurs (1750 mhz, 30 khz, 3 khz) 2khz 1khz 2800mhz +1khz +2khz v dd = 3v, v p = 5v i cp = 1ma pfd f requency = 1mhz loop b andwidth = 100khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 26 reference level = 10.3dbm output power db 0 50 70 80 90 10 30 60 40 20 100 85.2dbc/hz figure 11. adf4118 phase noise (2800 mhz, 1 mhz, 100 khz) 10db/division r l = 40dbc/hz rms noise = 1.552 100hz frequency offset from 2.8 ghz carrier 1mhz phase noise dbc/hz 40 70 80 90 100 50 60 110 120 130 140 1.55 rms figure 12. adf4118 integrated phase noise (2800 mhz, 1 mhz, 100 khz)
adf4116/ADF4117/adf4118 8 rev. 0 2mhz 1mhz +1mhz +2mhz v dd = 3v, v p = 5v i cp = 1ma pfd f requency = 1mhz loop b andwidth = 100khz res. bandwidth = 3khz video bandwidth = 3khz sweep = 1.4 seconds averages = 4 reference level = 9.3dbm output power db 0 50 70 80 90 10 30 60 40 20 100 2800mhz 77.3dbc figure 13. adf4118 reference spurs (2800 mhz, 1 mhz, 100 khz) phase detector frequency khz 1 10000 100 1000 175 phase noise dbc/hz 145 150 160 170 130 135 10 165 155 140 v dd = 3v v p = 5v figure 14. adf4118 phase noise (referred to cp out- put) vs. pfd frequency 40 phase noise dbc/hz 60 80 90 70 100 temperature c 200 20406080100 v dd = 3v v p = 5v figure 15. adf4118 phase noise vs. temperature (900 mhz, 200 khz, 20 khz) 40 first reference spur dbc 60 80 90 70 100 temperature c 20 0 20 40 60 80 100 v dd = 3v v p = 5v figure 16. adf4118 reference spurs vs. temperature (900 mhz, 200 khz, 20 khz) 0 first reference spur dbc 5 95 105 turning voltage 1 v dd = 3v v p = 5v 2345 85 75 65 55 45 35 25 15 5 figure 17. adf4118 reference spurs (200 khz) vs. v tune (900 mhz, 200 khz, 20 khz) phase noise dbc/hz 60 80 90 70 temperature c 0 20406080100 v dd = 3v v p = 5v figure 18. adf4118 phase noise vs. temperature (836 mhz, 30 khz, 3 khz)
adf4116/ADF4117/adf4118 9 rev. 0 first reference spur dbc 60 80 90 70 temperature c 0 20406080100 v dd = 3v v p = 5v 100 figure 19. adf4118 reference spurs vs. temperature (836 mhz, 30 khz, 3 khz) circuit description reference input section the reference input stage is shown below in figure 21. sw1 and sw2 are normally-closed switches. sw3 is normally-open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. buffer to r counter ref in 100k nc sw2 sw3 no nc sw1 power-down control figure 21. reference input stage rf input stage the rf input stage is shown in figure 22. it is followed by a 2- stage limiting ampli?r to generate the cml clock levels needed for the prescaler. av dd agnd 500 500 1.6v bias generator rf in a rf in b figure 22. rf input stage prescaler (p/p + 1) the dual modulus prescale (p/p + 1), along with the a and b counters, enables the large division ratio, n, to be realized, (n = pb + a). the dual-modulus prescaler takes the cml clock from the rf input stage and divides it down to a manageable frequency for the cmos a and b counters. the prescaler is programmable. it can be set in software to 8/9 for the adf4116, and set to 32/33 for the ADF4117 and adf4118. it is based on a synchronous 4/5 core. a and b counters the a and b cmos counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the pll feedb ack counter. the counters are speci?d to work when the prescaler output is 200 mhz or less. pulse swallow function the a and b counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by r. the equation for the vco frequency is as follows: f vco = [( p b ) + a ] f refin / r f vco output frequency of external voltage controlled oscilla- tor (vco). p preset modulus of dual modulus prescaler. b preset divide ratio of binary 13-bit counter (3 to 8191). a preset d ivide ratio of binary 5-bit swallow counter (0 to 31). f refin output frequency of the external reference frequency oscillator. r preset divide ratio of binary 14-bit programmable refer- ence counter (1 to 16383). r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the input clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. 13-bit b counter 5-bit a counter prescaler p/p + 1 from rf input stage modulus control n = bp + a load load to pfd figure 23. a and b counters 0 di dd ma 0.0 prescaler output frequency mhz 50 100 150 200 0.5 1.0 1.5 2.0 2.5 3.0 figure 20. di dd vs. prescaler output frequency (adf4116, ADF4117, adf4118)
adf4116/ADF4117/adf4118 10 rev. 0 phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 24 is a simpli?d schematic. the pfd includes a ?ed delay element which sets the width of the antibacklash pulse. this is typically 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function and gives a consis tent reference spur level. delay u3 clr1 q1 d1 cp down up hi u1 clr2 q2 d2 u2 hi n divider r divider v p charge pump cp gnd r divider cp output n divider figure 24. pfd simpli ed schematic and timing (in lock) muxout and lock detect the output multiplexer on the adf4116 family allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2 and m1 in the function latch. table vi shows the full truth table. figure 25 shows the muxout section in block diagram form. control mux dv dd muxout dgnd analog lock detect digital lock detect r counter output n counter output sdout figure 25. muxout circuit lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. it is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. it will stay set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. the n-channel open-drain analog lock detect should be oper- ated with an external pull-up resistor of 10 k ? nominal. when lock has been detected it is high with narrow low-going pulses. input shift register the adf4116 fam ily digital section in cludes a 21-bit input shift register, a 14-bit r counter and a?`-bit n counter, comprising a 5-bit a counter and a 13-bit b counter. data is clocked into the 21-bit shift register on each rising edge of clk. the data is clocked in msb ?st. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs db1, db0 as shown in the timing diagram of figure 1. the truth table for these bits is shown in table vii. table ii shows a summary of how the latches are programmed. table ii. c2, c1 truth table control bits c2 c1 data latch 0 0 r counter 0 1 n counter (a and b) 1 0 function latch 1 1 initialization latch
adf4116/ADF4117/adf4118 11 rev. 0 table iii. adf4116 family latch summary lock detect precision test mode bits db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 ldp t4 t3 t2 t1 r14 r13 r12 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 c2 (0) c1 (0) r9 14-bit reference counter, r control bits db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 g1 b13 b12 b11 b10 b9 b8 b7 b6 b5 b3 b2 b1 a5 a4 a3 a2 a1 c2 (0) c1 (1) b4 control bits 13-bit b counter 5-bit a counter cp gain db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 tc4 tc3 tc2 tc1 f6 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (0) control bits muxout control power- down 2 power- down 1 count reseter pd polarity fastlock enable cp three- state fastlock mode timer counter control db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 pd2 tc4 tc3 tc2 tc1 f6 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (1) control bits muxout control power- down 2 power- down 1 count reseter pd polarity fastlock enable cp three- state fastlock mode timer counter control reference counter latch ab counter latch function latch initialization latch reserved reserved pd2 x db20 x reserved xx x reserved reserved x x reserved xx x
adf4116/ADF4117/adf4118 12 rev. 0 table iv. reference counter latch map r14 0 0 0 0 1 1 1 1 r13 0 0 0 0 1 1 1 1 r12 0 0 0 0 1 1 1 1 r3 r2 r1 divide ratio 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 1 0 1 1 2 3 4 163 80 163 81 163 82 163 83 test mode bits should be set to 0000 for normal operation operation ldp 3 consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 5 consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 0 1 lock detect precision test mode bits db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 ldp t4 t3 t2 t1 r14 r13 r12 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 c2 (0) c1 (0) r9 14-bit reference counter, r control bits
adf4116/ADF4117/adf4118 13 rev. 0 table v. ab counter latch map current settings ldp 250 a 0 1 a5 x x x x a4 x x x x a3 0 0 1 1 a2 0 0 1 1 a1 0 1 0 1 a counter divide ratio 0 1 6 7 b13 0 0 0 0 1 1 1 1 b12 0 0 0 0 1 1 1 1 b11 0 0 0 0 1 1 1 1 b3 b2 b1 b counter divide ratio 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 1 0 1 not allowed not allowed 3 4 8188 8189 8190 8191 adf4116 a5 0 0 0 1 1 1 a4 0 0 0 1 1 1 a3 0 0 0 1 1 1 a2 0 0 1 0 1 1 a1 0 1 0 1 0 1 a counter divide ratio 0 1 2 29 30 31 ADF4117/adf4118 1ma n = bp + a, p is prescaler value. b must be greater than or equal to a. for continuously adjacent values of n x f ref , n min is (p 2 -p). db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 g1 b13 b12 b11 b10 b9 b8 b7 b6 b5 b3 b2 b1 a5 a4 a3 a2 a1 c2 (0) c1 (1) b4 control bits 13-bit b counter 5-bit a counter cp gain
adf4116/ADF4117/adf4118 14 rev. 0 table vi. function latch map m3 0 0 0 0 1 1 1 1 m2 0 0 1 1 0 0 1 1 m1 0 1 0 1 0 1 0 1 output three-state output digital lock detect (active high) n divider output av dd r divider output analog lock detect (n channel open drain) serial data output (inverse polarity of serial data input) dgnd tc4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tc3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 tc2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 tc1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 timeout (pfd cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 f1 0 1 counter operation normal r, a, b counters held in reset f2 0 1 pd polarity negative positive f3 0 1 charge pump output normal 3-state 0 1 1 1 ce pin pd2 pd1 mode x x 0 1 x 0 1 1 f6 x 0 1 fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 f4 0 1 1 asynchronous power-down normal operation asynchronous power-down synchronous power-down db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 tc4 tc3 tc2 tc1 f6 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (0) control bits muxout control power- down 2 power- down 1 count reseter pd polarity fastlock enable cp three- state fastlock mode timer counter control reserved reserved pd2 x db20 x reserved xx x
adf4116/ADF4117/adf4118 15 rev. 0 table vii. initialization latch map m3 0 0 0 0 1 1 1 1 m2 0 0 1 1 0 0 1 1 m1 0 1 0 1 0 1 0 1 output three-state output digital lock detect (active high) n divider output av dd r divider output analog lock detect (n channel open drain) serial data output (inverse polarity of serial data input) dgnd tc4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tc3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 tc2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 tc1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 timeout (pfd cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 f1 0 1 counter operation normal r, a, b counters held in reset f2 0 1 pd polarity negative positive f3 0 1 charge pump output normal three-state 0 1 1 1 ce pin pd2 pd1 mode asynchronous power-down normal operation asynchronous power-down synchronous power-down x x 0 1 x 0 1 1 f6 x 0 1 fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 f4 0 1 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db10 pd2 tc4 tc3 tc2 tc1 f6 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (1) control bits muxout control power- down 2 power- down 1 count reseter pd polarity fastlock enable cp three- state fastlock mode timer counter control reserved reserved x x reserved xx x
adf4116/ADF4117/adf4118 16 rev. 0 the function latch with c2, c1 set to 1, 0, the on-chip function latch will be pro- grammed. table vi shows the input data format for programming the function latch. counter reset db2 (f1) is the counter reset bit. when this is ?,?the r counter and the a, b counters are reset. for normal operation this bit should be ?.? upon powering up, the f1 bit needs to be disabled, the n counter resumes counting in ?lose?alignment with the r counter. (the maximum error is one prescaler cycle.) power-down db3 (pd1) and db19 (pd2) on the adf4116 family, provide programmable power-down modes. they are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of pd2, pd1. in the programmed asynchronous power-down, the device pow- ers down immediately after latching a ??into bit pd1, with the condition that pd2 has been loaded with a ?. in the programmed synchronous power-down, the device power down is gated by the charge pump to prevent unwanted fre- quency jumps. once the power-down is enabled by writing a ??into bit pd1 (on condition that a ??has also been loaded to pd2), then the device will go into power-down after the ?st successive charge pump event. when a power down is activated (either synchronous or asynchro- nous mode including ce-pin-activated power down), the following events occur: all active dc current paths are removed. the r, n and timeout counters are forced to their load state conditions. the charge pump is forced into three-state mode. the digital clock detect circuitry is reset. the rf in input is debiased. the oscillator input buffer circuitry is disabled. the input register remains active and capable of loading and latching data. muxout control the on-chip multiplexer is controlled by m3, m2, m1 on the adf4116 family. table vi shows the truth table. phase detector polarity db7 (f2) of the function latch sets the phase detector polarity. when the vco characteristics are positive this should be set to ?.?when they are negative it should be set to ?. charge pump three-state this bit puts the charge pump into three-state mode when pro- grammed to a ?.?it should be set to ??for normal operation. fastlock enable bit db9 of the function latch is the fastlock enable bit. only when this is ??is fastlock enabled. fastlock mode bit db11 of the function latch is the fastlock m ode bit. when fastlock is enabled, this bit determines which fastlock mode is used. if the fastlock mode bit is ??then fastlock mode 1 is selected and if the fastlock mode bit is ?,?then fastlock mode 2 is selected. if fastlock is not enabled (db9 = ??, then db11 (adf4116) determines the state of the fl o output. fl o state will be the same as that programmed to db11. fastlock mode 1 in the adf4116 family, the output level of fl o is programmed to a low state and the charge pump current is switched to the high value (1 ma). fl o is used to switch a resistor in the loop ?ter and ensure stability while in fastlock by altering the loop bandwidth. the device enters fastlock by having a ??written to the cp gain bit in the n register. the device exits fastlock by having a ??written to the cp gain bit in the n register. fastlock mode 2 in the adf4116 family, the output level of fl o is programmed to a low state and the charge pump current is switched to the high value (1 ma). fl o is used to switch a resistor in the loop ?ter and ensure stability while in fastlock by altering the loop bandwidth. the device enters fastlock by having a ??written to the cp gain bit in the n register. the device exits fastlock under the control of the timer counter. after the timeout period de ter- mined by the value in tc4?c1, the cp gain bit in the n register is automatically reset to ??and the device reverts to normal mode instead of fastlock. timer counter control in the adf4116 family, the user has the option of switching between two charge pump current values to speed up locking to a new frequency. when using the fastlock feature with the adf4116 family, the normal sequence of events is as follows: the user must make sure that fastlock is enabled. set db9 of the adf4116 family to ?.?the user must also choose which fastlock mode to use. as discussed in the previous section, f astlock mode 2 uses the values in the timer counter to deter mine the timeout period before reverting to normal mode operation after fastlock. fastlock mode 2 is chosen by setting db11 of the adf4116 family to ?. the user must also decide how long they want the high current (1 ma) to stay active before reverting to low current (250 a). this is controlled by the timer counter control bits db14 to db11 (tc4?c1) in the function latch. the truth table is given in table vi. now, when the user wishes to program a new output frequency, they can simply program the a, b counter latch with new values for a and b. at the same time they can set the cp gain bit to a ?,?which sets the charge pump 1 ma for a period of time de ter- mined by tc4?c1. when this time is up, the charge pump current reverts to 250 a. at the same time the cp gain bit in the a, b counter latch is reset to 0 and is now ready for the next time that the user wishes to change the frequency again.
adf4116/ADF4117/adf4118 17 rev. 0 the initialization latch when c2, c1 = 1, 1 then the initialization latch is pro grammed. this is essentially the same as the function latch (programmed when c2, c1 = 1, 0). however, when the initialization latch is programmed there is a additional internal reset pulse applied to the r and n counters. this pulse ensures that the n counter is at load point when the n counter data is latched and the device will begin counting in close phase alignment. if the latch is programmed for synchronous power-down (ce pin is high; pd1 bit is high; pd2 bit is low), the internal pulse also triggers this power-down. the prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. when the ?st n counter data is latched after initialization, the internal reset pulse is again activated. however, successive n counter loads after this will not trigger the internal reset pulse. device programming after initial power-up after initially powering up the device, there are three ways to program the device. initialization latch method apply v dd . program the initialization latch (?1?in 2 lsbs of input word). make sure that f1 bit is programmed to ?.?then do an r load (?0?in 2 lsbs). then do an n load (?1?in 2 lsbs). when the initialization latch is loaded, the following occurs: 1. the function latch contents are loaded. 2. an internal pulse resets the r, n and timeout counters to load state conditions and also three-states the charge pump. note that the prescaler bandgap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. 3. latching the ?st n counter data after the initialization word will activate the same internal reset pulse. successive n loads will not trigger the internal reset pulse unless there is another initialization. the ce pin method apply v dd . bring ce low to put the device into power-down. this is an asynchronous power-down in that it happens immediately. program the function latch (10). program the r counter latch (00). program the n counter latch (01). bring ce high to take the device out of power-down. the r and n counter will now resume counting in close alignment. note that after ce goes high, a duration of 1 s may be required for the prescaler bandgap voltage and oscillator input buffer bias to reach steady state. ce can be used to power the device up and down in order to check for channel activity. the input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after v cc was initially applied. the counter reset method apply v dd . do a function latch load (?0?in 2 lsbs). as part of this, load ??to the f1 bit. this enables the counter reset. do an r counter load (?0?in 2 lsbs). do an n counter load (?1 in 2 lsbs). do a function latch load (?0?in 2 lsbs). as part of this, load ??to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initial- ization method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. the counter reset method requires an extra func- tion latch load compared to the initialization latch method.
adf4116/ADF4117/adf4118 18 rev. 0 applications section local oscillator for gsm base station transmitter figure 26 shows the ADF4117/adf4118 being used with a vco to produce the lo for a gsm base station transmitter. the reference input signal is applied to the circuit at fref in and, in this case, is terminated in 50 ? . typical gsm system would have a 13 mhz tcxo driving the reference input without any 50 ? termination. in order to have a channel spacing of 200 khz (the gsm standard), the reference input must be divided by 65, using the on-chip reference divider of the ADF4117/adf1118. the charge pump output of the ADF4117/adf1118 (pin 2) drives the loop ?ter. in calculating the loop ?ter component values, a num ber of items need to be considered. in this example, the loop ?ter was designed so that the overall phase margin for the system would be 45 degrees. other pll system speci?a- tions are given below: k d = 1 ma k v = 12 mhz/v loop bandwidth = 20 khz f ref = 200 khz n = 4500 extra reference spur attenuation = 10 db all of these speci?ations are needed and used to come up with the loop ?ter components values shown in figure 27. the loop ?ter output drives the vco, which, in turn, is fed back to the rf input of the pll synthesizer and also drives the rf output terminal. a t-circuit con?uration provides 50 ? matching between the vco output, the rf output and the rf in terminal of the synthesizer. in a pll system, it is important to know when the system is in lock. in figure 26, this is accomplished by using the muxout signal from the synthesizer. the muxout pin can be pro- grammed to monitor various internal signals in the synthesizer. one of these is the ld or lock-detect signal. vco190-902t v cc 18 100pf 100pf 18 18 rf out v dd v p av dd dv dd ADF4117/ adf4118 v p 0.15nf 620pf 3.3k 71516 2 14 6 5 8 fref in 1000pf 1000pf 51 muxout lock detect 51 100pf 34 9 100pf cpgnd agnd dgnd rf in a rf in b ce clk data le spi-compatible serial bus decoupling capacitors (10 f/10pf) on av dd , dv dd , v p of the ADF4117/adf4118 and on v cc of the vco190-902t have been omitted from the diagram to aid clarity. fl o cp 10k 1.5nf 27k ref in figure 26. local oscillator for gsm base station shutdown circuit the attached circuit in figure 27 shows how to shut down both the adf4116 family and the accompanying vco. the adg702 switch goes open circuit when a logic 1 is applied to the in input. the low-cost switch is available in both sot-23 and micro soic packages. direct conversion modulator in some applications a direct conversion architecture can be used in base station transmitters. figure 28 shows the combination available from adi to implement this solution. the circuit diagram shows the ad9761 being used with the ad8346. the use of dual integrated dacs such as the ad9761 with speci?d 0.02 db and 0.004 db gain and offset match- ing characteristics ensures minimum error contribution (over temperature) from this portion of the signal chain. the local oscillator (lo) is implemented using the ADF4117/ adf4118. in this case, the osc 3b1-13m0 provides the stable 13 mhz reference frequency. the system is designed for a 200 khz channel spacing and an output center frequency of 1960 mhz. the target application is a wcdma base sta- tion transmitter. t ypical phase noise performance from this lo is ?5 dbc/hz at a 1 khz offset. the lo port of the ad8346 is driven in single-ended fashion. loin is ac-coupled to ground with the 100 pf capacitor and loip is driven through the ac- coupling capacitor from a 50 ? source. an lo drive level of between ? dbm and ?2 dbm is required. the circuit of figure 28 gives a typical level of ? dbm. the rf output is designed to drive a 50 ? load but must be ac-coupled as shown in figure 28. if the i and q inputs are driven in quadrature by 2 v p-p signals, the resulting output power will be around ?0 dbm.
adf4116/ADF4117/adf4118 19 rev. 0 interfacing the adf4116 family has a simple spi-compatible serial inter- face for writing to the device. sclk, sdata and le control the data transfer. when le (latch enable) goes high, the 24 bits which have been clocked into the input register on each rising edge of sclk will get transferred to the appropriate latch. see figure 1 for the timing diagram and table ii for the latch truth table. v dd v p av dd dv dd adf4116/ ADF4117/ adf4118 v p 10k vco v cc gnd 18 100pf 100pf 18 18 rf out 71516 2 1 6 5 8 fref in 51 100pf 349 100pf cpgnd agnd dgnd rf in a rf in b decoupling capacitors and interface signals have been omitted from the diagram to aid clarity. fl o cp ce power-down control v dd s in d gnd loop filter adg702 ref in figure 27. local oscillator shutdown circuit low-pass filter r set adf4118 vco190-1960t 18 100pf 18 ref in 100pf rf in a rf in b cp serial digital nterface tcxo osc 3b1-13m0 100pf 51 18pf 1k 10k 6.8nf 18 rf out power supply connections and decoupling capacitors are omitted from diagram for clarity. ad9761 t x dac refio fs adj modulated digital data qoutb iouta ioutb qouta low-pass filter ibbp qbbp ibbp qbbp ad8346 loin loip vout 100pf 100pf 2k 0.1 f 100pf 680pf figure 28. direct conversion transmitter solution the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 833 khz or one update every 1.2 microseconds. this is certainly more than adequate for systems which will have typical lock times in hun- dreds of microseconds.
adf4116/ADF4117/adf4118 20 rev. 0 aduc812 interface figure 29 shows the interface between the adf4116 family and the aduc812 microconverter. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4116 family needs a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written the le input should be brought high to complete the transfer. sclock mosi i/o ports aduc812 sclk sdata le ce muxout (lock detect) adf4116/ ADF4117/ adf4118 figure 29. aduc812 to adf4116 family interface on ?st applying power to the adf4116 family, it needs three writes (one each to the r counter latch, the n counter latch and the initialization latch) for the output to become active. i/o port lines on the aduc812 are also used to control power- down (ce input) and to detect lock (muxout con?ured as lock detect and polled by the port input). when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed will be 166 khz. adsp-2181 interface figure 30 shows the interface between the adf4116 family and the adsp-21xx digital signal processor. the adf4116 family needs a 21-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate fram- ing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. sclk dt i/o flags adsp-21xx sclk sdata le ce muxout (lock detect) adf4116/ ADF4117/ adf4118 tfs figure 30. adsp-21xx to adf4116 family interface set up the word length for 8 bits and use three memory loca- tions for each 24-bit word. to program each 21-bit latch, store the three 8-bit bytes, enable the autobuffered mode and then write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. outline dimensions dimensions shown in inches and (mm). chip scale (cp-20) 1 20 5 6 10 16 11 15 bottom view (rotated 180 ) 0.014 (0.35) 45 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) 0.079 (2.0) ref 0.079 (2.0) ref detail e 0.020 (0.5) ref lead pitch 0.0079 (0.20) ref 0.0083 (0.211) 0.0079 (0.200) 0.0077 (0.195) seating plane 0.039 (1.00) 0.035 (0.90) 0.031 (0.80) 0.159 (4.05) 0.157 (4.00) 0.156 (3.95) top view 0.159 (4.05) 0.157 (4.00) 0.156 (3.95) 0.0059 (0.15) ref 0.011 (0.275) 0.010 (0.250) 0.009 (0.225) 0.0059 (0.15) ref 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) lead option detail e controlling dimensions are in millimeters thin shrink small outline (ru-16) 16 9 8 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 c3767 5 4/00 (rev. 0) printed in u.s.a.

▲Up To Search▲

Price & Availability of ADF4117

	To Download ADF4117 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .